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Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.

Y. Li, Y. Li, I. Wey, J. Hu, F. Yang, X. Zeng, X. Jiang, and J. Chen. IEEE J. Solid State Circuits, 53 (8): 2389-2398 (2018)

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Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

A novel wavelet method for noise analysis of nonlinear circuits.X. Zeng, B. Liu, J. Tao, C. Chiang, and D. Zhou. ASP-DAC, page 471-476. ACM Press, (2005)A single event upset tolerant latch with parallel nodes.C. Liu, N. Liu, Z. Lin, X. Wu, C. Peng, Q. Zhao, X. Li, J. Chen, X. Zeng, and X. Hu. IEICE Electron. Express, 16 (11): 20190208 (2019)Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.Z. Gao, J. Tao, D. Zhou, and X. Zeng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3144-3148 (2020)C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.W. Zeng, H. Zhu, X. Zeng, D. Zhou, R. Liu, and X. Li. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (6): 899-912 (2017)Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.Y. Li, Z. Bai, Y. Su, and X. Zeng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1571-1582 (2008)Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network.S. Zhang, W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng. DATE, page 1463-1468. IEEE, (2019)High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.M. Wang, C. Yan, X. Li, D. Zhou, and X. Zeng. IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 806-819 (2017)An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.X. Ge, F. Yang, H. Zhu, X. Zeng, and D. Zhou. IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 611-623 (2019)A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.M. Li, G. Huang, X. Wu, L. Qian, X. Zeng, and D. Zhou. Sci. China Inf. Sci., 59 (8): 082401:1-082401:16 (2016)Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.X. Zhou, F. Yang, H. Zhou, M. Gong, H. Zhu, Y. Zhang, and X. Zeng. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (11): 2227-2235 (2014)

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Disambiguation of "Zeng, Xuan"

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Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.

Please choose a person to relate this publication to

Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zeng, Xuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.

Please choose a person to relate this publication to

Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method.