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A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)Hybrid 8-bit Floating Point (HFP8) Training and Inference for Deep Neural Networks., , , , , , , , and . NeurIPS, page 4901-4910. (2019)A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm2., , , , , , , , , and 5 other author(s). ISSCC, page 400-402. IEEE, (2012)DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference., , , , , , and . ARITH, page 92-95. IEEE, (2019)Improved Techniques for Quantizing Deep Networks with Adaptive Bit-Widths., , , , , , , and . WACV, page 946-956. IEEE, (2024)COMQ: A Backpropagation-Free Algorithm for Post-Training Quantization., , , , , , and . CoRR, (2024)A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 48 (1): 244-254 (2013)Ultra-Low Precision 4-bit Training of Deep Neural Networks., , , , , , , , , and . NeurIPS, (2020)Deep Compression of Pre-trained Transformer Models., , , , , , , and . NeurIPS, (2022)An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors., , , , , , , , , and 1 other author(s). VLSIC, page 192-. IEEE, (2015)