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Asymmetric clock driver for improved power and noise performances.

, , , и . ISCAS, стр. 893-896. IEEE, (2007)

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Victor Manuel Bastidas Valencia

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William Valencia

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Другие публикации лиц с тем же именем

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , и . PATMOS, том 1918 из Lecture Notes in Computer Science, стр. 316-326. Springer, (2000)Selective Clock-Gating for Low-Power Synchronous Counters., , , и . J. Low Power Electron., 1 (1): 11-19 (2005)Hamming-Code Based Fault Detection Design Methodology for Block Ciphers., , , , , и . ISCAS, стр. 1-5. IEEE, (2020)Modeling of real bistables in VHDL., , , , и . EURO-DAC, стр. 460-465. IEEE Computer Society, (1993)Asymmetric clock driver for improved power and noise performances., , , и . ISCAS, стр. 893-896. IEEE, (2007)New CMOS VLSI linear self-timed architectures., , , , , и . ASYNC, стр. 14-23. IEEE Computer Society, (1995)Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher., , , , и . DCIS, стр. 1-6. IEEE, (2018)Fault attack on FPGA implementations of Trivium stream cipher., , и . ISCAS, стр. 562-565. IEEE, (2016)Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1., , и . PATMOS, том 2451 из Lecture Notes in Computer Science, стр. 448-457. Springer, (2002)A switching noise vision of the optimization techniques for low-power synthesis., , , и . ECCTD, стр. 156-159. IEEE, (2007)