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Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.

, , , , and . HPSR, page 1-6. IEEE, (2018)

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FlexTCAM: Beyond Memory Based TCAM Emulation on FPGAs., , and . NFV-SDN, page 110-113. IEEE, (2020)Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays., , , , and . HPSR, page 1-6. IEEE, (2018)Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs., , , , , , , and . ACM Trans. Embed. Comput. Syst., 22 (4): 76:1-76:19 (July 2023)SqueezeNIC: Low-Latency In-NIC Compression for Distributed Deep Learning., , , , and . NAIC, page 61-68. ACM, (2024)Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs., , , and . IEEE Embed. Syst. Lett., 14 (1): 35-38 (2022)An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs., , , , and . Microelectron. Reliab., (2017)CO-19 PDB 2.0: A Comprehensive COVID-19 Database with Global Auto-Alerts, Statistical Analysis, and Cancer Correlations., , , , , , , , and . Database J. Biol. Databases Curation, (January 2024)On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs., and . AHS, page 9-14. IEEE, (2013)An error-detection and self-repairing method for dynamically and partially reconfigurable systems., , and . ETS, page 1-7. IEEE Computer Society, (2013)Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs., , and . FPL, page 1-6. IEEE, (2014)