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SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash Memory., , , and . ACM Great Lakes Symposium on VLSI, page 255-260. ACM, (2018)A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface., , , , , , , , , and 24 other author(s). ISSCC, page 136-137. IEEE, (2022)A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory., , , , , and . IEICE Trans. Electron., 93-C (2): 182-186 (2010)A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory., , , , , , , , , and 7 other author(s). VLSIC, page 132-133. IEEE, (2012)Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories., , , , , , and . IEEE J. Solid State Circuits, 45 (10): 2165-2172 (2010)Flashdefibrillator: a data recovery technique for retention failures in NAND flash memory., , and . NVMSA, page 1-6. IEEE, (2015)13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate., , , , , , , , , and 35 other author(s). ISSCC, page 218-220. IEEE, (2020)Improving performance and lifetime of NAND storage systems using relaxed program sequence., , , , and . DAC, page 63:1-63:6. ACM, (2016)