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Disambiguation of "Onodera, Hidetoshi"

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A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking.

, , , , , and . A-SSCC, page 1-4. IEEE, (2015)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics., , , , , , , and . ICRC, page 1-8. IEEE, (2018)An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing., , , , and . ICRC, page 1-6. IEEE, (2018)BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing., , , , , and . ASP-DAC, page 203-209. ACM, (2019)Post-layout transistor sizing for power reduction in cell-based design., and . ASP-DAC, page 359-365. ACM, (2001)Statistical gate delay model for Multiple Input Switching., , and . ASP-DAC, page 286-291. IEEE, (2008)A functional memory type parallel processor for vector quantization., , , , and . ASP-DAC, page 665-666. IEEE, (1997)A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime., , , , , , and . FPL, page 1-4. IEEE, (2006)Performance optimization by track swapping on critical paths utilizing random variations for FPGAS., , , and . FPL, page 503-506. IEEE, (2008)Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies., , and . ASP-DAC, page 589-590. ACM, (2003)A performance optimization method by gate sizing using statistical static timing analysis., and . ISPD, page 111-116. ACM, (2000)