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Disambiguation of "Rhee, Woogeun"

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An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation.

, , , , and . MWSCAS, page 1-4. IEEE, (2016)

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Sascha Rhee

Hanjo Rhee

Sora Rhee

Kyu Ho Rhee

Jong Il Rhee

 

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An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution., , and . IEEE J. Solid State Circuits, 37 (4): 515-520 (2002)A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator., , and . IEEE J. Solid State Circuits, 35 (10): 1453-1460 (2000)All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs., , , and . ISSCC, page 176-595. IEEE, (2007)A high efficiency robust IR-UWB receiver design for high data rate CM-range communications., , , and . ISCAS, page 1901-1904. IEEE, (2014)A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL., , , and . ISCAS, page 1440-1443. IEEE, (2014)A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS., , and . ESSCIRC, page 53-56. IEEE, (2023)A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS., , , and . ICTA, page 76-77. IEEE, (2021)A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection., , , and . CICC, page 1-2. IEEE, (2022)9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications., , , , , and . ISSCC, page 160-161. IEEE, (2014)Experimental Analysis of Substrate Noise Effect on PLL Performance., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (7): 638-642 (2008)