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Disambiguation of "Ker, Ming-Dou"

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Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.

, , , , , and . ISQED, page 267-272. IEEE Computer Society, (2001)

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Keqi Dou

Keqi Dou

Wei Dou

Huating Dou

Shouzhi Dou

 

Other publications of authors with the same name

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2013)Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits., , , and . VLSI-DAT, page 1-4. IEEE, (2013)New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process., and . VLSI-DAT, page 1-4. IEEE, (2012)Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., and . ISCAS (1), page 297-300. IEEE, (2003)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., and . SoCC, page 33-36. IEEE, (2013)Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs., , , and . IEEE J. Solid State Circuits, 46 (2): 537-545 (2011)Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications., and . MWSCAS, page 1-4. IEEE, (2018)A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process., and . IEEE Trans. Biomed. Circuits Syst., 10 (6): 1087-1099 (2016)High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process., , and . NEWCAS, page 125-128. IEEE, (2012)Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process., , , , , and . ISQED, page 267-272. IEEE Computer Society, (2001)