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Disambiguation of "Harjani, Ramesh"

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A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS.

, and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (11): 1053-1057 (2015)

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Ramesh Ummanni

Ramesh Boggula

Ramesh Sharma

Ramesh Sheth

Ramesh Samanta

 

Other publications of authors with the same name

Design of Low Power Integrated Radios for Emerging Standards, and . Springer, (2020)System-level design for test of fully differential analog circuits., , and . IEEE J. Solid State Circuits, 31 (10): 1526-1534 (1996)Gain Calibration Technique for Increased Resolution in FRC Data Converters., and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (11): 1200-1204 (2006)A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS., , , , , , and . VLSIC, page 150-. IEEE, (2015)Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%)., and . ISCAS, page 1975-1978. IEEE, (2010)A novel noise optimization design technique for radio frequency low noise amplifiers., , and . ISCAS (1), page 209-212. IEEE, (2003)Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection., and . ISCAS (4), page 786-789. IEEE, (2001)A CMOS high efficiency +22 dBm linear power amplifier., and . CICC, page 557-560. IEEE, (2004)On the selection of on-chip inductors for the optimal VCO design., , and . CICC, page 277-280. IEEE, (2004)A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS., and . CICC, page 1-4. IEEE, (2019)