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Instruction Level Mechanisms for Accurate Real-time Task Scheduling., and . RTSS, page 209-215. IEEE Computer Society, (1986)Technologies for reducing power.. ICSAMOS, IEEE, (2010)Analysis and Design of Latch-Controlled Synchronous Digital Circuits., , and . DAC, page 111-117. IEEE Computer Society Press, (1990)Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009.. IEEE Micro, 30 (1): 8-11 (2010)Analyzing the scalability of SIMD for the next generation software defined radio., , , , and . ICASSP, page 5388-5391. IEEE, (2008)Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability., , , , , , , , and . DAC, page 76:1-76:6. ACM, (2016)Challenges and Opportunities for Extremely Energy-Efficient Processors., and . IEEE Micro, 30 (4): 20-24 (2010)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)Introduction to the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques., , , and . ACM Trans. Embed. Comput. Syst., 22 (2): 27:1-27:3 (March 2023)Ada on hypercube., and . C³P, page 399-408. ACM, (1988)