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Disambiguation of "Dreslinski, Ronald G."

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Low power interconnects for SIMD computers.

, , , , , , and . DATE, page 600-605. IEEE, (2011)

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Giuseppe G G Manzardo

Ronald Keipert

Acmella ciliata (H.B.K.) Cassini: phytochemische und enzymatische Untersuchungen, galenische Präformulierungen. FU Berlin, (2009)

G Lüers

G Baumann

G Schweitzer

 

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An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 56 (4): 1071-1081 (2021)Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores., , , , , , , , , and 5 other author(s). ISSCC, page 190-192. IEEE, (2012)FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)., , , , , , , , , and 5 other author(s). IEEE Des. Test, 41 (1): 70-80 (February 2024)Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor., , , , , , and . PACT, page 148-159. ACM, (2022)A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 202-203. IEEE, (2022)WarpPool: sharing requests with inter-warp coalescing for throughput processors., , , , , , and . MICRO, page 433-444. ACM, (2015)Mint: An Accelerator For Mining Temporal Motifs., , , , , , , , , and 1 other author(s). MICRO, page 1270-1287. IEEE, (2022)Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture., , , , , , , and . ISCAS, page 1-5. IEEE, (2020)Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor., , , , , , , , , and 33 other author(s). ISCAS, page 443-447. IEEE, (2022)A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning., , , , , , , , and . IISWC, page 87-100. IEEE, (2021)