Author of the publication

AVC encoder.

J. Liu, X. Chen, Y. Fan, and X. Zeng. VLSI-SoC, page 434-439. IEEE, (2011)

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Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Aiqun Zeng

Yan Zeng

Other publications of authors with the same name

A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture.G. Tang, M. e Jing, X. Zeng, and Y. Fan. ISCAS, page 1-5. IEEE, (2019)A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.Y. Liu, Y. Li, X. Cheng, J. Han, and X. Zeng. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (4): 1639-1648 (April 2023)A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis.Q. Zhang, Y. Chen, S. Li, X. Zeng, and K. Parhi. IEEE Trans. Circuits Syst., 67-I (12): 5429-5442 (2020)A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting.L. Fang, Y. Li, Y. Zhang, S. Zhang, X. Zeng, Z. Hong, and J. Xu. ESSCIRC, page 554-557. IEEE, (2022)A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages.P. Cao, D. Lu, J. Xu, X. Zeng, and Z. Hong. ESSCIRC, page 277-280. IEEE, (2022)A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise.M. Li, J. Wang, X. Cheng, and X. Zeng. ISCAS, page 2876-2880. IEEE, (2022)A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process.X. Hu, Y. Wang, J. Feng, Z. Ma, X. Zeng, and Y. Xie. ISCAS, page 2438-2442. IEEE, (2022)NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition.F. Tian, J. Jiang, J. Liang, Z. Zhang, J. Shi, C. Fang, H. Wu, X. Xue, and X. Zeng. ISCAS, page 2695-2699. IEEE, (2022)A Decision-Based CORDIC Hardware for Arc Tangent Calculation.H. Wu, L. Lin, H. Sun, X. Zeng, and Y. Chen. ASICON, page 1-4. IEEE, (2023)Knowledge Distillation for U-Net Based Image Denoising.W. Chen, L. Peng, Y. Huang, M. e Jing, and X. Zeng. ASICON, page 1-4. IEEE, (2021)

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Disambiguation of "Zeng, Xiaoyang"

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A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.

Please choose a person to relate this publication to

Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Aiqun Zeng

Yan Zeng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zeng, Xiaoyang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.

Please choose a person to relate this publication to

Xiaoyang Wang

Xiaoyang Gao

Jian Zeng

Aiqun Zeng

Yan Zeng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder.