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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , и . ASICON, стр. 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , и . ASICON, стр. 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , и . ASICON, стр. 1-4. IEEE, (2013)Low-complexity two-stage timing acquisition scheme for UWB communications., , и . WTS, стр. 53-56. IEEE, (2008)A common flexible architecture for Turbo/LDPC codes., , , , и . ISOCC, стр. 54-57. IEEE, (2011)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , и . ISCAS, стр. 349-352. IEEE, (2013)An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems., , , , и . ISCAS, стр. 1516-1519. IEEE, (2012)Low power design for FIR filter., , , и . ASICON, стр. 1-4. IEEE, (2013)Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation., , , и . SiPS, стр. 151-156. IEEE, (2007)