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Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.

H. Takahashi, K. Boateng, and Y. Takamatsu. Asian Test Symposium, page 108-112. IEEE Computer Society, (1998)

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Yuzo Sugimoto

Other publications of authors with the same name

On the fault diagnosis in the presence of unknown fault models using pass/fail information.T. Seiyama, H. Takahashi, Y. Higami, K. Yamazaki, and Y. Takamatsu. ISCAS (3), page 2987-2990. IEEE, (2005)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.Y. Higami, K. Saluja, H. Takahashi, S. ya Kobayashi, and Y. Takamatsu. ASP-DAC, page 659-664. IEEE, (2006)Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.H. Takahashi, K. Boateng, Y. Takamatsu, and N. Yanagida. Asian Test Symposium, page 341-346. IEEE Computer Society, (1999)Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.H. Takahashi, M. Phadoongsidhi, Y. Higami, K. Saluja, and Y. Takamatsu. Asian Test Symposium, page 63-. IEEE Computer Society, (2001)Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.H. Takahashi, Y. Yamamoto, Y. Higami, and Y. Takamatsu. Asian Test Symposium, page 216-221. IEEE Computer Society, (2004)Test research in Japan.H. Fujiwara, Y. Takamatsu, T. Nanya, T. Yamada, H. Tamamoto, and K. Furuya. IEEE Des. Test, 5 (5): 60-79 (1988)Test generation for scan design circuits with tri-state modules and bidirectional terminals.T. Ogihara, S. Murai, Y. Takamatsu, K. Kinoshita, and H. Fujiwara. DAC, page 71-78. ACM/IEEE, (1983)Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits.Y. Higami, S. ya Kobayashi, and Y. Takamatsu. DELTA, page 431-433. IEEE Computer Society, (2002)Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.K. Keller, H. Takahashi, K. Le, K. Saluja, and Y. Takamatsu. Asian Test Symposium, page 242-247. IEEE Computer Society, (2002)A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.H. Takahashi, K. Boateng, and Y. Takamatsu. VTS, page 64-69. IEEE Computer Society, (1999)

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Disambiguation of "Takamatsu, Yuzo"

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Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.

Please choose a person to relate this publication to

Yuzo Sugimoto

Other publications of authors with the same name

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BibSonomy

Disambiguation of "Takamatsu, Yuzo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.

Please choose a person to relate this publication to

Yuzo Sugimoto

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.