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A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.

S. Wang, S. Yang, H. Chen, C. Yang, and J. Wu. J. Signal Process. Syst., 57 (2): 195-211 (2009)

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Lin Yang

Yang Lin

Chia-Lin Lee

Chia-Ching Lin

Other publications of authors with the same name

Power gating strategies on GPUs.P. Wang, C. Yang, Y. Chen, and Y. Cheng. ACM Trans. Archit. Code Optim., 8 (3): 13:1-13:25 (2011)DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.W. Lin, H. Cheng, C. Yang, M. Lin, K. Lien, H. Hu, H. Chang, H. Li, M. Chang, Y. Tsou and 1 other author(s). ACM Trans. Embed. Comput. Syst., 21 (3): 24:1-24:29 (2022)Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.N. Dong, H. Cheng, C. Yang, B. Lin, and H. Li. NVMSA, page 1-7. IEEE, (2022)Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.C. Ji, L. Wang, Q. Li, C. Gao, L. Shi, C. Yang, and C. Xue. NVMSA, page 1-6. IEEE, (2019)FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems.H. Wan, X. Sun, Y. Cui, C. Yang, T. Kuo, and C. Xue. APSys, page 9-16. ACM, (2021)Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning.Z. Ke, H. Cheng, C. Yang, and H. Huang. ISPASS, page 276-287. IEEE, (2021)DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.M. Lin, H. Cheng, W. Lin, T. Yang, I. Tseng, C. Yang, H. Hu, H. Chang, H. Li, and M. Chang. ICCAD, page 31. ACM, (2018)A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.Y. Lin, C. Yang, H. Li, and C. Wang. ACM Trans. Design Autom. Electr. Syst., 22 (2): 27:1-27:22 (2017)LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling.Z. Ke, H. Cheng, and C. Yang. CoRR, (2018)EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.R. Liu, M. Chuang, C. Yang, C. Li, K. Ho, and H. Li. DAC, page 145:1-145:6. ACM, (2014)

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Disambiguation of "Yang, Chia-Lin"

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A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.

Please choose a person to relate this publication to

Lin Yang

Lin Yang

Yang Lin

Chia-Lin Lee

Chia-Ching Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Chia-Lin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.

Please choose a person to relate this publication to

Lin Yang

Lin Yang

Yang Lin

Chia-Lin Lee

Chia-Ching Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.