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Disambiguation of "Chang, Meng-Fan"

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DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.

, , , , , , , , , and . ICCAD, page 31. ACM, (2018)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (11): 2786-2795 (2015)8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 58 (1): 303-315 (2023)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)An embedded ReRAM using a small-offset sense amplifier for low-voltage operations., , , and . VLSI-DAT, page 1-4. IEEE, (2015)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 120-. IEEE, (2019)ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration., , , , , , , , , and 11 other author(s). MICRO, page 763-783. IEEE, (2022)Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices., and . ISOCC, page 164-165. IEEE, (2019)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices., , , , , , , , , and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 662-666 (2019)Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination., , , , , , , and . DAC, page 38:1-38:6. ACM, (2014)