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Efficient Test Set Modification for Capture Power Reduction., , , , , , и . J. Low Power Electron., 1 (3): 319-330 (2005)Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns., , , , , и . J. Low Power Electron., 8 (2): 248-258 (2012)A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application., , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 287-291 (2019)Efficient Guided-Probe Fault Location Method for Sequential Circuits., , , и . IEICE Trans. Inf. Syst., 78-D (2): 122-129 (1995)Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1767-1776 (2009)A Method to Detect Bit Flips in a Soft-Error Resilient TCAM., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1185-1196 (2018)LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults., , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications., , , , , , , и . DAC, стр. 1-6. IEEE, (2020)Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications., , , и . DATE, стр. 1679-1684. IEEE, (2019)Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets., , , , , , и . IEEE Access, (2019)