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Disambiguation of "Wei, Gu-Yeon"

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MASR: A Modular Accelerator for Sparse RNNs.

, , , , , , , and . PACT, page 1-14. IEEE, (2019)

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Wei Gu

Wei Gu

Sang-Chun Yeon

Yeon Ha

Wei Wei

 

Other publications of authors with the same name

Structured Compression by Unstructured Pruning for Sparse Quantized Neural Networks., , , , , and . CoRR, (2019)Network Pruning for Low-Rank Binary Indexing., , , , and . CoRR, (2019)EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP., , , , , , , , and . CoRR, (2020)DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications., , , and . IEEE J. Solid State Circuits, 53 (9): 2722-2731 (2018)An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery., , , and . IEEE J. Solid State Circuits, 44 (11): 3120-3130 (2009)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , and . IEEE J. Solid State Circuits, 43 (4): 855-863 (2008)Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators., , , , , , , and . DAC, page 1:1-1:6. ACM, (2017)A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs., , , , , , , , , and . IEEE J. Solid State Circuits, 58 (2): 569-581 (February 2023)Digital wireline and PLL techniques., and . CICC, IEEE, (2009)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)