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Disambiguation of "Flatresse, Philippe"

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Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.

, , , , , , , and . ISCAS, page 1452-1455. IEEE, (2013)

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Philippe Kersting

Philippe Bopp

Philippe Zysset

Philippe Dreuw

Philippe Moisan

 

Other publications of authors with the same name

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology., , , , , , and . VLSI-SoC, page 168-173. IEEE, (2013)Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec., , , , , , , and . ISSCC, page 336-337. IEEE, (2011)Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2388-2400 (2017)Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI., , , , , , , and . ISCAS, page 1452-1455. IEEE, (2013)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Converting an Embedded Low-Power SRAM from Bulk to PD-SOI., and . MTDT, page 163-167. IEEE Computer Society, (2002)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology., , , , , , , , , and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs.. ISLPED, page 127-130. ACM, (2014)UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency., , and . DATE, page 952-957. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Bottom-up digital system-level reliability modeling., , , , , , , , and . CICC, page 1-4. IEEE, (2011)