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Disambiguation of "Dehan, Morin"

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Impact of fin shape variability on device performance towards 10nm node.

, , , , , , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Gabriel Morin

Helga Morin

Dieter Morin

Luce Morin

Rudy Morin

 

Other publications of authors with the same name

Low-cost feedback-enabled LNAs in 45nm CMOS., , , , and . ESSCIRC, page 100-103. IEEE, (2009)Identifying the Bottlenecks to the RF Performance of FinFETs., , , , , , and . VLSI Design, page 111-116. IEEE Computer Society, (2010)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)The Potential of FinFETs for Analog and RF Circuit Applications., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (11): 2541-2551 (2007)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)FinFET RF receiver building blocks operating above 10 GHz., , , , , , , and . ESSCIRC, page 360-363. IEEE, (2009)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions., , , , , , , , , and 8 other author(s). CICC, page 1-4. IEEE, (2010)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)FinFET technology for analog and RF circuits., , , , , , , and . ICECS, page 182-185. IEEE, (2007)