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Disambiguation of "Rao, Rajeev R."

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Modeling and Analysis of Parametric Yield under Power and Performance Constraints.

, , , and . IEEE Des. Test Comput., 22 (4): 376-385 (2005)

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Yadlapalli Venkateswara Rao

Bharathi Vasudeva Rao

Balakrishna Rao

Sonti Venkata Suryanarayana Rao

Nidamboor Vasanth Rao

 

Other publications of authors with the same name

Statistical estimation of leakage current considering inter- and intra-die process variation., , , and . ISLPED, page 84-89. ACM, (2003)Circuit optimization techniques to mitigate the effects of soft errors in combinational logic., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)Bus encoding for total power reduction using a leakage-aware buffer configuration., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (12): 1376-1383 (2005)Modeling and Analysis of Parametric Yield under Power and Performance Constraints., , , and . IEEE Des. Test Comput., 22 (4): 376-385 (2005)IBM POWER7+ design for higher frequency at fixed power., , , , , , , , and . IBM J. Res. Dev., (2013)Soft error reduction in combinational logic using gate resizing and flipflop selection., , and . ICCAD, page 502-509. ACM, (2006)Leakage-and crosstalk-aware bus encoding for total power reduction., , , and . DAC, page 779-782. ACM, (2004)Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 468-479 (2007)An efficient static algorithm for computing the soft error rates of combinational circuits., , , and . DATE, page 164-169. European Design and Automation Association, Leuven, Belgium, (2006)Analytical yield prediction considering leakage/performance correlation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1685-1695 (2006)