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A Sound and Complete Axiomatization of Majority-n Logic., , , and . IEEE Trans. Computers, 65 (9): 2889-2895 (2016)Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache., , , and . ISQED, page 163-170. IEEE, (2014)A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)., , and . FPGA, page 281. ACM, (2016)Synthesis of low-power selectively-clocked systems from high-level specification., and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 311-321 (2000)3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)Optimization of Reliability and Power Consumption in Systems on a Chip., , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 237-246. Springer, (2005)A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication., , , , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 232-250. Springer, (2008)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Pattern-based FPGA logic block and clustering algorithm., , and . FPL, page 1-4. IEEE, (2014)Parallel vs. serial inter-plane communication using TSVs., , and . LASCAS, page 1-5. IEEE, (2014)