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Disambiguation of "Degawa, Katsuhiko"

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Phase-based alignment of two signals having partially overlapped spectra.

, , , , , and . ICASSP, page 3337-3340. IEEE, (2009)

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Katsuhiko Kondo

 

Other publications of authors with the same name

Phase-based alignment of two signals having partially overlapped spectra., , , , , and . ICASSP, page 3337-3340. IEEE, (2009)A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions., , , , and . ISMVL, page 269-274. IEEE Computer Society, (2004)Application of a continuous-time level crossing quantization method for timing noise measurements., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2011)High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language., , , , and . ISMVL, page 112-117. IEEE Computer Society, (2008)A new method for measuring alias-free aperture jitter in an ADC output., , , , , and . ITC, page 1-6. IEEE, (2015)A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic., , and . ISMVL, page 213-220. IEEE Computer Society, (2003)Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams., , , and . ISMVL, page 31. IEEE Computer Society, (2007)A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors., , , , , and . ISMVL, page 19. IEEE Computer Society, (2006)A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic., , , , and . ISMVL, page 262-268. IEEE Computer Society, (2004)An equivalent-time and clocked approach for continuous-time quantization., , , , , , , and . ISCAS, page 2529-2532. IEEE, (2011)