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Disambiguation of "Lagos, Jorge"

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A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC.

, , , , , and . ESSCIRC, page 207-210. IEEE, (2021)

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Flavio Lagos Galván

Soledad Lagos Kassai

Mariana Lagos-Quintana

Markus Lagos

Sonia Lagos-Witte

 

Other publications of authors with the same name

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier., , , , , , , and . IEEE J. Solid State Circuits, 57 (6): 1673-1683 (2022)A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 57 (4): 1112-1124 (2022)A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm., , , , , , and . ISSCC, page 68-70. IEEE, (2019)A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers., , , , and . IEEE J. Solid State Circuits, 54 (3): 646-658 (2019)A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS., , , , and . ESSCIRC, page 389-392. IEEE, (2023)A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion., , , , , , and . ISSCC, page 58-60. IEEE, (2019)16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation., , , , , , , and . ISSCC, page 254-256. IEEE, (2020)A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS., , , , and . IEEE J. Solid State Circuits, 54 (2): 403-416 (2019)An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)