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Disambiguation of "Pan, David Z."

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Redundant Local-Loop Insertion for Unidirectional Routing.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1113-1125 (2017)

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David Tse-chien Pan

Z Taufig

Petra Pan

Xiaoqing Pan

Weiqing Pan

 

Other publications of authors with the same name

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes., , , , and . IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 185-196 (2010)Redundant Local-Loop Insertion for Unidirectional Routing., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1113-1125 (2017)OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1618-1629 (2016)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 55 (12): 3248-3259 (2020)A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier., , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2564-2574 (September 2023)An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback., , and . IEEE J. Solid State Circuits, 55 (5): 1337-1350 (2020)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)