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Disambiguation of "Ryu, Seung-Tak"

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An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC.

, , , , , and . CICC, page 1-2. IEEE, (2023)

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Seung-Hun Ryu

Seung-Min Ryu

Jung-Hun Seung

Ryu Yoshiwhara

Hosuk Ryu

 

Other publications of authors with the same name

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 794-798 (2016)An incremental zoom sturdy MASH ADC., , , and . MWSCAS, page 1013-1016. IEEE, (2017)A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC., , , , , , and . A-SSCC, page 1-3. IEEE, (2023)A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC., , , and . VLSI Circuits, page 72-. IEEE, (2019)23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface., , , , , , , , , and 2 other author(s). ISSCC, page 402-403. IEEE, (2014)A 10b 50MS/s pipelined ADC with opamp current reuse., , and . ISSCC, page 792-801. IEEE, (2006)A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (9): 2532-2542 (2019)A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration., , , , and . VLSI Circuits, page 138-. IEEE, (2019)A novel readout IC with high noise immunity for charge-based touch screen panels., , , , , , , , and . CICC, page 1-4. IEEE, (2010)Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 52 (12): 3115-3118 (2017)