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True Random Number Generation using Latency Variations of Commercial MRAM Chips., , , and . ISQED, page 510-515. IEEE, (2021)System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning., and . ACM Great Lakes Symposium on VLSI, page 697-702. ACM, (2023)A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs., , and . VTS, page 1-6. IEEE Computer Society, (2015)Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation., , , , and . ACM Trans. Design Autom. Electr. Syst., 25 (4): 35:1-35:22 (2020)Analogy-Guided Evolutionary Pretraining of Binary Word Embeddings., , , and . AACL/IJCNLP (1), page 683-693. Association for Computational Linguistics, (2022)An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs., , , , , and . ATS, page 269-274. IEEE Computer Society, (2014)Design of a digital IP for 3D-IC die-to-die clock synchronization., , , and . ISCAS, page 1-4. IEEE, (2017)Design of near threshold All Digital Delay Locked Loops., and . SoCC, page 137-142. IEEE, (2012)Special Session: Reliability Analysis for AI/ML Hardware., , , , , , and . VTS, page 1-10. IEEE, (2021)Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware., , , , , , , and . VTS, page 1-12. IEEE, (2022)