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Disambiguation of "Ha, Kyung-Soo"

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

, , , , , , , , , , , , , , , , and . ISSCC, page 314-315. IEEE, (2016)

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Soo Kyung Kim

Kyung Ha Bahlig

Kyung-Taek Ha

Soo-Kyung Seo

Kyung-Hyo Ha

 

Other publications of authors with the same name

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme., , , , , , , and . ISSCC, page 410-411. IEEE, (2013)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process., , , , , , , , , and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation., , , , , , , , , and 16 other author(s). ISSCC, page 430-431. IEEE, (2014)Charge-pump reducing current mismatch in DLLs and PLLs., and . ISCAS, IEEE, (2006)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution., , , , , , , , , and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver., , and . ISCAS, IEEE, (2006)A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces., , , , , , and . ISSCC, page 138-139. IEEE, (2009)