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pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi, C. Shin, S. Kim, B. Kim, S. Ko, K. Park, S. Jang, and G. Jin. ISSCC, page 314-315. IEEE, (2016)

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Soo-Young Kim

Young-Soo Chang

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits.I. Yi, S. Bae, Y. Sohn, J. Sim, and H. Park. ISOCC, page 192-195. IEEE, (2012)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM.J. Moon, H. Yoo, H. Choi, I. Park, S. Kang, J. Kim, H. Chung, K. Kim, D. Lee, K. Song and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.J. Bae, Y. Sohn, S. Bae, K. Park, J. Choi, Y. Jun, J. Sim, and H. Park. CICC, page 1-4. IEEE, (2010)Design and fabrication of a vibration sensor using a conductive ball.Y. Cho, S. Jang, Y. Sohn, and S. Choi. Microelectron. J., 38 (3): 416-421 (2007)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.S. Bae, Y. Sohn, K. Park, K. Kim, D. Chung, J. Kim, S. Kim, M. Park, J. Lee, S. Bang and 16 other author(s). ISSCC, page 278-279. IEEE, (2008)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.Y. Kim, S. Lee, S. Bae, Y. Sohn, J. Lee, J. Choi, H. Park, and J. Sim. ISSCC, page 136-138. IEEE, (2012)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.J. Kim, S. Kang, S. Lee, H. Kim, W. Song, Y. Ro, S. Lee, D. Wang, H. Shin, B. Phuah and 10 other author(s). HCS, page 1-26. IEEE, (2021)

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

Please choose a person to relate this publication to

Soo-Young Kim

Young-Soo Chang

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sohn, Young-Soo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

Please choose a person to relate this publication to

Soo-Young Kim

Young-Soo Chang

Young-Soo Han

Young-Taek Sohn

Hae-Young Sohn

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.