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pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi, C. Shin, S. Kim, B. Kim, S. Ko, K. Park, S. Jang, and G. Jin. ISSCC, page 314-315. IEEE, (2016)

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Chang-Su Ahn

Jong-Su Ahn

Min-Su Kim

Iau-Min Su

Min-su Chang

Other publications of authors with the same name

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.Y. Kim, H. Kwon, S. Doo, Y. Eom, Y. Kim, M. Ahn, Y. Kim, S. Jung, S. Do, C. Lee and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.Y. Kim, H. Kim, J. Choi, M. Ahn, D. Lee, S. Cho, D. Park, Y. Park, M. Jang, Y. Kim and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.J. Baek, C. Lee, K. Kim, D. Moon, G. Cha, J. Heo, M. Ahn, D. Kim, J. Song, S. Kwon and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.H. Joo, S. Bae, Y. Sohn, Y. Kim, K. Ha, M. Ahn, Y. Kim, Y. Kim, J. Kim, W. Choi and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.C. Lee, M. Ahn, D. Moon, K. Kim, Y. Eom, W. Lee, J. Kim, S. Yoon, B. Choi, S. Kwon and 6 other author(s). VLSIC, page 182-. IEEE, (2015)

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Disambiguation of "Ahn, Min-Su"

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

Please choose a person to relate this publication to

Chang-Su Ahn

Jong-Su Ahn

Min-Su Kim

Iau-Min Su

Min-su Chang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ahn, Min-Su"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.

Please choose a person to relate this publication to

Chang-Su Ahn

Jong-Su Ahn

Min-Su Kim

Iau-Min Su

Min-su Chang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.