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Matrix Codes for Reliable and Cost Efficient Memory Chips.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 420-428 (2011)

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An application specific processor for implementing stack filters., , and . ASAP, page 196-199. IEEE, (1993)Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems., , and . ICPP (1), page 326-330. Pennsylvania State University Press, (1990)P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP., , , and . ISQED, page 176-183. IEEE, (2010)Program Fault Tolerance Based on Memory Access Behavior., and . FTCS, page 426-435. IEEE Computer Society, (1991)Modified Tree Structure for Location Management in Mobile Environments., , and . INFOCOM, page 530-537. IEEE Computer Society, (1995)A Multiprocessor Network Suitable for Single-Chip VLSI Implementation., and . ISCA, page 328-337. ACM, (1984)Design of Reversible Finite Field Arithmetic Circuits with Error Detection., , , and . VLSI Design, page 453-459. IEEE Computer Society, (2008)A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM., , , and . VLSI Design, page 45-50. IEEE Computer Society, (2010)Recovery in Multicomputers with Finite Error Detection Latency., , and . ICPP (2), page 206-210. CRC Press, (1994)Job Scheduling in Mesh Multicomputers., and . ICPP (2), page 251-258. CRC Press, (1994)