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Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks., , , and . CoRR, (2021)High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension., , , , , , , , , and 1 other author(s). ASAP, page 164-169. IEEE Computer Society, (2017)Runtime rule-reconfigurable high throughput NIPS on FPGA., , , , and . FPT, page 251-254. IEEE, (2017)FPGA IP for Real-time 4K HDR Image Decoding in VR Devices., , , , , and . LASCAS, page 101-104. IEEE, (2019)A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform., , and . DSD, page 472-478. IEEE Computer Society, (2018)High performance flow matching architecture for OpenFlow data plane., , , , and . NFV-SDN, page 186-191. IEEE, (2016)Real time all intra HEVC HD encoder on FPGA., , , , and . ASAP, page 191-195. IEEE Computer Society, (2016)Hybrid Software Defined Networking Controller., , , , and . DCNET, page 77-84. SciTePress, (2017)Impact of ICT on learning and teaching., and . ISTAS, page 1-10. IEEE, (2008)FPAA and FPGA based universal sensor node design., , , , and . ICST, page 1-6. IEEE, (2017)