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Disambiguation of "Kossel, Marcel A."

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A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.

, , , , , , , , , , , , and . ESSCIRC, page 309-312. IEEE, (2016)

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Albrecht Kossel

Elke Kossel

Albrecht Kossel

Friedrich Kossel

Elmar Kossel

 

Other publications of authors with the same name

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology., , , , , , , and . ESSCIRC, page 67-70. IEEE, (2021)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement., , , , , , and . ISSCC, page 2082-2091. IEEE, (2006)A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 44 (11): 2901-2910 (2009)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , and 6 other author(s). A-SSCC, page 239-240. IEEE, (2019)