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Adaptive high-speed and ultra-low power optical interconnect for data center communications., , , , , , , и . ICTON, стр. 1-4. IEEE, (2017)Analysis of parameter-independent PLLs with bang-bang phase-detectors., , , и . ICECS, стр. 299-302. IEEE, (1998)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , и . ISSCC, стр. 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , и . ISSCC, стр. 358-360. IEEE, (2018)F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets., , , , , и . ISSCC, стр. 529-532. IEEE, (2021)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS., , , , , и . IEEE J. Solid State Circuits, 44 (11): 2901-2910 (2009)Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee., , и . ISSCC, стр. 124-125. IEEE, (2021)A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement., , , , , , и . ISSCC, стр. 2082-2091. IEEE, (2006)