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Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.

J. Vieira, E. Giacomin, Y. Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P. Gaillardon. VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 257-278. Springer, (2019)

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João Paulo Vieira Pinheiro

Gil dos Santos Guerreiro João

João Barros

João Fonseca

João Carreira

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A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.J. Vieira, E. Giacomin, Y. Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P. Gaillardon. VLSI-SoC, page 160-165. IEEE, (2019)gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation.J. Vieira, N. Roma, G. Falcão, and P. Tomás. IEEE Comput. Archit. Lett., 23 (1): 1-4 (January 2024)The DOTPAR Project: Towards a Framework Supporting Domain Oriented Tools for Parallel and Distributed Processing.J. Cunha, P. Medeiros, J. Lourenço, V. Duarte, J. Vieira, B. Moscão, D. Pereira, and R. Vaz. HPCN Europe, volume 1401 of Lecture Notes in Computer Science, page 952-954. Springer, (1998)An Architecture for Capturing and Synchronizing Heart Rate and Body Motion for Stress Inference.J. Lopes, J. Vieira, I. Van-Deste, and R. Lopes. SeGAH, page 1-7. IEEE, (2023)gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM.J. Vieira, N. Roma, G. Falcão, and P. Tomás. SBAC-PAD, page 41-50. IEEE, (2022)A Framework to support Parallel and Distrubuted Debugging.J. Cunha, J. Lourenço, J. Vieira, B. Moscão, and D. Pereira. HPCN Europe, volume 1401 of Lecture Notes in Computer Science, page 708-717. Springer, (1998)Automatic Annotation of Heart Rate Sequences.J. Lopes, J. Vieira, A. Antunes, L. Deusdado, and R. Lopes. SeGAH, page 1-6. IEEE, (2023)SleeveAR: Augmented Reality for Rehabilitation using Realtime Feedback.M. Sousa, J. Vieira, D. Medeiros, A. Arsénio, and J. Jorge. IUI, page 175-185. ACM, (2016)Exploiting Compute Caches for Memory Bound Vector Operations.J. Vieira, N. Roma, P. Tomás, P. Ienne, and G. Fernandes. SBAC-PAD, page 197-200. IEEE, (2018)Decision Tree Learner in the Presence of Domain Knowledge.J. Vieira, and C. Antunes. CSWS, volume 480 of Communications in Computer and Information Science, page 42-55. Springer, (2014)

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Disambiguation of "Vieira, João"

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Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.

Please choose a person to relate this publication to

João Paulo Vieira Pinheiro

Gil dos Santos Guerreiro João

João Barros

João Fonseca

João Carreira

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vieira, João"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.

Please choose a person to relate this publication to

João Paulo Vieira Pinheiro

Gil dos Santos Guerreiro João

João Barros

João Fonseca

João Carreira

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.