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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , и 10 other автор(ы). DATE, стр. 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , и . NANOARCH, стр. 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?, , , , и . LASCAS, стр. 1-4. IEEE, (2017)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , и 9 other автор(ы). IMW, стр. 1-4. IEEE, (2023)A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM., , , , , , и . VLSI-SoC, стр. 1-6. IEEE, (2024)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , и . DATE, стр. 1634-1639. IEEE, (2018)Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , и . DATE, стр. 298-301. IEEE, (2020)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , и . DATE, стр. 1-6. IEEE, (2021)A Dataset Generation Toolbox for Dynamic Security Assessment: On the Role of the Security Boundary., , , , и . CoRR, (января 2025)A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology., и . ISCAS, стр. 1906-1909. IEEE, (2008)