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Disambiguation of "Tsai, Jeng-Liang"

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HiSIM: hierarchical interconnect-centric circuit simulator.

, , and . ICCAD, page 489-496. IEEE Computer Society / ACM, (2004)

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Shyi-Jeng Tsai

Wen-Liang Tsai

Liang Liang

Jih-Jau Jeng

Yang-Mo Paul Jeng

 

Other publications of authors with the same name

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis., and . ICCAD, page 575-581. IEEE Computer Society, (2005)Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method., , , and . ISCAS, IEEE, (2006)Sensitivity guided net weighting for placement driven synthesis., , and . ISPD, page 124-131. ACM, (2004)Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops., , , , and . ASP-DAC, page 941-946. IEEE, (2006)False Path and Clock Scheduling Based Yield-Aware Gate Sizing., , , and . VLSI Design, page 423-426. IEEE Computer Society, (2005)HiSIM: hierarchical interconnect-centric circuit simulator., , and . ICCAD, page 489-496. IEEE Computer Society / ACM, (2004)A yield improvement methodology using pre- and post-silicon statistical clock scheduling., , , and . ICCAD, page 611-618. IEEE Computer Society / ACM, (2004)Thermal and Power Integrity Based Power/Ground Networks Optimization., , and . DATE, page 830-835. IEEE Computer Society, (2004)Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling., and . ASP-DAC, page 1168-1171. ACM Press, (2005)Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time., , and . ISPD, page 166-173. ACM, (2003)