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NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks.

, , , , and . ICCAD, page 58:1-58:9. ACM, (2022)

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Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)A lightweight face detector by integrating the convolutional neural network with the image pyramid., , , and . Pattern Recognit. Lett., (2020)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)FACCU: Enable Fast Accumulation for High-Speed DSP Systems., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (12): 4634-4638 (2022)Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1708-1714 (March 2024)Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm., , and . CoRR, (2019)Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks., , , , and . SiPS, page 117-122. IEEE, (2021)Segmented successive cancellation list polar decoding with joint BCH-CRC codes., , , , and . ACSSC, page 1509-1513. IEEE, (2017)A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator., , and . IEEE Trans. Circuits Syst., 67-I (10): 3484-3497 (2020)