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A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems., and . IEEE Trans. Multi Scale Comput. Syst., 2 (4): 291-296 (2016)On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly., and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (1): 31-35 (2009)Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT., , and . J. Electron. Test., 32 (5): 587-599 (2016)Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates., , , and . J. Electron. Test., 25 (1): 39-54 (2009)On the Constant Diagnosability of Baseline Interconnection Networks., and . IEEE Trans. Computers, 39 (12): 1485-1488 (1990)An Architecture and an Interconnection Scheme for Time-Sliced Buses in Real-Time Processing., , and . RTSS, page 20-27. IEEE Computer Society, (1986)A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation., , , , , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 1853-1866 (2021)Approximate computing using frequency upscaling., , , and . IET Circuits Devices Syst., 13 (7): 1018-1026 (2019)Editor's Note.. IEEE Trans. Computers, 56 (6): 721-726 (2007)Selective Neuron Re-Computation (SNRC) for Error-Tolerant Neural Networks., , and . IEEE Trans. Computers, 71 (3): 684-695 (2022)