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Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.

, , and . ERSA, page 291-294. CSREA Press, (2009)

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Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Advanced Devices and Architectures., , and . Principles and Structures of FPGAs, Springer, (2018)FPGA-Based Acceleration of Word2vec using OpenCL., , , , , , and . ISCAS, page 1-5. IEEE, (2019)An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture., , , and . ERSA, page 271-274. CSREA Press, (2010)Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2576-2586 (2013)