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Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1814-1827 (2011)

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PEPR: Pseudo-Exhaustive Physically-Aware Region Testing., , , , and . ITC, page 314-323. IEEE, (2022)Diagnostic Test Generation for Arbitrary Faults., and . ITC, page 1-9. IEEE Computer Society, (2006)An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis., and . ITC, page 1-9. IEEE Computer Society, (2008)Testability of Convergent Tree Circuits., and . IEEE Trans. Computers, 45 (8): 950-963 (1996)Universal fault simulation using fault tuples., and . DAC, page 786-789. ACM, (2000)Efficient Test Chip Design via Smart Computation., , , , and . ACM Trans. Design Autom. Electr. Syst., 28 (2): 22:1-22:31 (March 2023)DREAMS: DFM rule EvAluation using manufactured silicon., , , , , and . ICCAD, page 99-106. IEEE, (2013)Controlling DPPM through Volume Diagnosis., , , , and . VTS, page 134-139. IEEE Computer Society, (2009)Physically-Aware N-Detect Test Relaxation., , and . VTS, page 197-202. IEEE Computer Society, (2009)Failure modes for stiction in surface-micromachined MEMS., , and . ITC, page 551-556. IEEE Computer Society, (1998)