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Disambiguation of "Fernández, Francisco V."

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Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.

, , , , and . VLSI-SoC, page 267-271. IEEE, (2006)

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Francisco Fernández Klett

Francisco Fernandez Fernandez

José Francisco Fernández Dámaso

Bárbara Fernández Fernández

N V Fernandez Villalobos

 

Other publications of authors with the same name

Introduction to the special issue on SMACD 2015., , and . Integr., (2016)Reliability simulation for analog ICs: Goals, solutions, and challenges., , , , , , , and . Integr., (2016)A simplification before and during generation methodology for symbolic large-circuit analysis., , , , and . ICECS, page 81-84. IEEE, (1998)Chaotic Image Encryption Using Hopfield and Hindmarsh-Rose Neurons Implemented on FPGA., , , , , , , and . Sensors, 20 (5): 1326 (2020)A template router., , and . ECCTD, page 334-337. IEEE, (2011)Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks., , , , , , , , and . SMACD, page 1-4. IEEE, (2017)Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs., , , , , , , , and . SMACD, page 1-164. IEEE, (2018)A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array., , , , , and . SMACD, page 1-4. IEEE, (2023)Accuate simplification of large symbolic formulae., , , and . ICCAD, page 318-321. IEEE Computer Society / ACM, (1992)Improving the reliability of SRAM-based PUFs in the presence of aging., , , , , and . DTIS, page 1-6. IEEE, (2020)