From post

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS.

, , , , , , и . ISSCC, стр. 410-411. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Factors Influencing the Learning Performance of u-Learning Systems., и . ICEIS (5), стр. 352-358. (2008)Understanding users in consumer electronics experience design., , и . CHI Extended Abstracts, стр. 189-194. ACM, (2006)An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS., , , , и . MWSCAS, стр. 1005-1009. IEEE, (2023)A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller., , , , , , , , , и 1 other автор(ы). VLSI Technology and Circuits, стр. 150-151. IEEE, (2022)Recognizing Cultural Diversity in Digital Television User Interface Design., и . HCI (3), том 4552 из Lecture Notes in Computer Science, стр. 902-908. Springer, (2007)The Enhancement Mechanisms of SiOx Hardness via Manipulation of Oxygen Content., , , , , , , , , и 6 other автор(ы). IRPS, стр. 10. IEEE, (2024)A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE., , , , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2677-2681 (2022)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS., , , , , , и . ISSCC, стр. 410-411. IEEE, (2023)A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS., , , , , , и . ISOCC, стр. 127-128. IEEE, (2021)Dynamic Adaptive Architecture for Self-adaptation in VideoConferencing System., , и . PCM (2), том 3768 из Lecture Notes in Computer Science, стр. 36-47. Springer, (2005)