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Computationally-redundant energy-efficient processing for y'all (CREEPY).

, , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)

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System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)Compilers for Instruction-Level Parallelism., , , , , and . Computer, 30 (12): 63-69 (1997)Rebooting Computers to Avoid Meltdown and Spectre., , , and . Computer, 51 (4): 74-77 (2018)A Power Model for Register-Sharing Structures., and . DIPES, volume 271 of IFIP, page 131-142. Springer, (2008)Modeling Value Speculation: An Optimal Edge Selection Problem., , and . IEEE Trans. Computers, 52 (3): 277-292 (2003)Parallel Pattern Detection for Architectural Improvements., , and . HotPar, USENIX Association, (2011)Systematic Computer Architecture Prototyping. University of Illinois Urbana-Champaign, USA, (1992)Adaptive Mode Control: A Static-Power-Efficient Cache Design., , , and . IEEE PACT, page 61-70. IEEE Computer Society, (2001)A Fast Interrupt Handling Scheme for VLIW Processors., , , , , and . IEEE PACT, page 136-141. IEEE Computer Society, (1998)Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors., and . MICRO, page 82-92. ACM/IEEE Computer Society, (1999)