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Using branch handling hardware to support profile-driven optimization., , and . MICRO, page 12-21. ACM / IEEE Computer Society, (1994)Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors., and . MICRO, page 82-92. ACM/IEEE Computer Society, (1999)Modeling Value Speculation: An Optimal Edge Selection Problem., , and . IEEE Trans. Computers, 52 (3): 277-292 (2003)A Power Model for Register-Sharing Structures., and . DIPES, volume 271 of IFIP, page 131-142. Springer, (2008)Parallel Pattern Detection for Architectural Improvements., , and . HotPar, USENIX Association, (2011)Path Prediction for High Issue-Rate Processors., , and . IEEE PACT, page 178-188. IEEE Computer Society, (1997)Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors., , and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 192-203. Springer, (2001)High-speed formal verification of heterogeneous coherence hierarchies., , , and . HPCA, page 566-577. IEEE Computer Society, (2013)Experimental Insights from the Rogues Gallery., , , , , and . ICRC, page 80-87. IEEE, (2019)System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)