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Optimizing Reconfigurable Recurrent Neural Networks., , , , , , , and . FCCM, page 10-18. IEEE, (2020)Memory-Efficient Architecture for Accelerating Generative Networks on FPGA., , , , , , , and . FPT, page 30-37. IEEE, (2018)Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator., , , , , , and . ASP-DAC, page 250-255. IEEE, (2022)Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs., , , , , and . FPT, page 301. IEEE, (2020)A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks., , , , , , , and . FPT, page 20-28. IEEE, (2020)Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation., , , , , and . FPL, page 287-294. IEEE Computer Society, (2018)Efficient Weight Reuse for Large LSTMs., , , , , , and . ASAP, page 17-24. IEEE, (2019)A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA., , , , , , , and . FPT, page 14-21. IEEE, (2018)Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM., , , , , and . FPT, page 379-382. IEEE, (2019)Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations., , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (12): 3387-3399 (2022)