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Disambiguation of "Matsuzawa, Akira"

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A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS.

, , and . ESSCIRC, page 151-154. IEEE, (2017)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Hayashima

Akira Yasui

 

Other publications of authors with the same name

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs., , and . IEICE Trans. Electron., 96-C (4): 577-585 (2013)22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers., , , , and . ISSCC, page 388-389. IEEE, (2014)Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A CMOS Smart Image Sensor LSI for Focal-Plane Compression., , , , , , , and . ASP-DAC, page 339-340. IEEE, (1998)A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio., , , , and . ASP-DAC, page 103-104. IEEE, (2008)A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS., , and . ESSCIRC, page 151-154. IEEE, (2017)Radio receiver front-end using time-based all-digital ADC (TAD)., , , , , , , , , and 3 other author(s). ICECS, page 471-473. IEEE, (2014)RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers., , , , , , and . IEICE Trans. Electron., 91-C (6): 854-861 (2008)Analog IC Technologies for Future Wireless Systems.. IEICE Trans. Electron., 89-C (4): 446-454 (2006)