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Optimizing redundancy design for chip-multiprocessors for flexible utility functions.

, and . ITC, page 1-8. IEEE Computer Society, (2014)

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Design and test of latch-based circuits to maximize performance, yield, and delay test quality., and . ITC, page 94-103. IEEE Computer Society, (2010)ERTG: A test generator for error-rate testing., and . ITC, page 1-10. IEEE Computer Society, (2007)Switch-level delay test of domino logic circuits., , and . ITC, page 367-376. IEEE Computer Society, (2001)Optimizing redundancy design for chip-multiprocessors for flexible utility functions., and . ITC, page 1-8. IEEE Computer Society, (2014)BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level., and . Asian Test Symposium, page 244-252. IEEE Computer Society, (1998)Analysis of Ground Bounce in Deep Sub-Micron Circuits., , and . VTS, page 110-116. IEEE Computer Society, (1997)A New March Test for Process-Variation Induced Delay Faults in SRAMs., , , , , , and . Asian Test Symposium, page 115-122. IEEE Computer Society, (2013)Efficient Trojan Detection via Calibration of Process Variations., and . Asian Test Symposium, page 355-361. IEEE Computer Society, (2012)BIST Test Pattern Generators for Stuck-Open and Delay Testing., and . EDAC-ETC-EUROASIC, page 289-296. IEEE Computer Society, (1994)Theory of redundancy for logic circuits to maximize yield/area., , , and . ISQED, page 663-671. IEEE, (2012)