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Autonomous Secure Remote Attestation even when all Used and to be Used Digital Keys Leak.

, , , , and . IACR Cryptol. ePrint Arch., (2021)

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A framework to accelerate sequential programs on homogeneous multicores., , , and . VLSI-SoC, page 344-347. IEEE, (2013)SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors., and . IEEE Comput. Archit. Lett., 21 (2): 129-132 (July 2022)ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes., , , and . ACM Trans. Archit. Code Optim., 20 (3): 32:1-32:24 (September 2023)CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM., , , , , , , , , and 1 other author(s). ICCD, page 280-289. IEEE, (2022)Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware., , and . ISQED, page 1-6. IEEE, (2022)Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors., and . SEED, page 203-209. IEEE, (2021)Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems., , and . HPEC, page 1-7. IEEE, (2021)ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor., and . HOST, page 192-202. IEEE, (2021)A self-adaptive system architecture to address transistor aging., and . DATE, page 81-86. IEEE, (2009)POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms., , , and . PACT, page 495-496. IEEE, (2019)