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Disambiguation of "Lee, Won"

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A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.

, , , , , , , , , , , , , , , , , and . ISSCC, page 406-407. IEEE, (2023)

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Chul-Won Lee

Jae-Won Lee

Seung-Won Lee

Seok Won Lee

Jong-Won Lee

 

Other publications of authors with the same name

Improved Spatiotemporal Noise Reduction for Very Low-Light Environments., and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (9): 888-892 (2016)OutlierD: an R package for outlier detection using quantile regression on mass spectrometry data., , , , and . Bioinform., 24 (6): 882-884 (2008)Detection and tracking for the awareness of surroundings of a ship based on deep learning., , , , , , and . J. Comput. Des. Eng., 8 (5): 1407-1430 (2021)Enabling technologies for AI empowered 6G massive radio access networks., , , , , , , , , and 7 other author(s). ICT Express, 9 (3): 341-355 (2023)Managing Fault Tolerance Information in Multi-agents Based Distributed Systems., , , , , , and . IDEAL, volume 2690 of Lecture Notes in Computer Science, page 104-108. Springer, (2003)A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 461-464. IEEE, (2016)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 231-242 (January 2024)Process variation tolerant all-digital multiphase DLL for DDR3 interface., , , , , , and . CICC, page 1-4. IEEE, (2010)A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection., , , , , , , , , and 8 other author(s). ISSCC, page 406-407. IEEE, (2023)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme., , , , , , , , , and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)